Showing posts with label VHDL Modeling and Logic Synthesis. Show all posts
Showing posts with label VHDL Modeling and Logic Synthesis. Show all posts
Sunday, November 4, 2012
Topics Covered
Introduction to VHDL. Basic VHDL constructs. Design of combinational logic (adders, multipliers, comparators, multiplexers/ demultiplexers, ALUs etc.) and sequential logic (flip-flops, registers, shift registers, random number generators, counters, FSMs etc.) with behavioral VHDL descriptions. Use of an industrial EDA tool for functional and post-route simulations, logic synthesis and automatic place and route. Writing testbenches. Design of FSMs. Converting algorithms to hardware using ASM charts and top-down design methodologies with CPLDs and FPGAs as target technologies. Emphasis on FSM design techniques. Controller-datapath partitioning. Algorithms that describe datapath elements. Microcontrollers. Design of simple and RISC processors. Pipelining.
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