Topics Covered

Review of FET amplifiers: Passive and active loads and frequency limitation. Current mirror: Basic, cascode and active current mirror. Differential Amplifier: Introduction, large and small signal analysis, common mode analysis and differential amplifier with active load. Noise: Introduction to noise, types, representation in circuits, noise in single stage and differential amplifiers and bandwidth. Band-gap references: Supply voltage independent biasing, temperature independent biasing, proportional to absolute temperature current generation and constant transconductance biasing. Switch capacitor circuits: Sampling switches, switched capacitor circuits including unity gain buffer, amplifier and integrator. Phase Locked Loop (PLL): Introduction, basic PLL and charge pumped PLL.

Phase Locked Loop (PLL)

Fig 1 : Block diagram of a PLL frequency multiplier

Phase Locked Loops (PLL) circuits are used for frequency control.  They can be configured as frequency multipliers, demodulators, tracking generators or clock recovery circuits. Each of these applications demands different characteristics but they all use the same basic circuit concept. Figure 1 contains a block diagram of a basic PLL frequency multiplier.  The operation of this circuit is typical of all phase locked loops.  It is basically a feedback control system that controls the phase of a voltage controlled oscillator (VCO). The  input signal is applied to one input of a phase detector.  The other input is connected to the output of a divide by N counter.  Normally the frequencies of both signals will be nearly the same.  The output of the phase detector is a voltage proportional to the phase difference between the two inputs.  This signal is applied to the loop filter.  It is the loop filter that determines the dynamic characteristics of the PLL.  The filtered signal controls the VCO.  Note that the output of the VCO is at a frequency that is N times the input supplied to the frequency reference input. This output signal is sent back to the phase  detector  via the divide by N counter. Normally the loop filter is designed to match the characteristics  required  by the application of the PLL. If the PLL is to acquire and track a signal the bandwidth of the loop filter will be greater than if it expects a fixed input frequency. The frequency range which the PLL will accept  and lock on is called the capture range.  Once the PLL is locked and tracking a signal the range of frequencies that the PLL will follow is called the tracking range. Generally the tracking range is larger than the capture range. The loop filter also determines how fast the signal frequency can change and still maintain lock. This is the maximum slewing rate.  The narrower the  loop filter bandwidth the smaller the achievable phase error.  This comes at the expense of slower response and reduced capture range.