Topics Covered

Physical defects in VLSI Circuits. Complexity and economics of testing. Fault models: Stuck-at Stack-on, Stack-open, bridging and delay faults. Testing combinational logic circuits : terminologies path sesicization, fanout and reconvergence, fault matrix , fault collapsing . test generation using D-algorithm,  Boolean difference and other methods. Testing sequential logic circ its : problems and remedies . Testability of different types of CMOS circuits for various faults . test invalidation. Robustly testable CMOS circuits . Test generation for static and dynamic CMOS. Design for testability: different techniques of enhancing testability scan design techniques, built-in self (BIST) Built-in current sensors (BICS) for IDDQ testing of CMOS circuits. Error detecting codes and self-checking circuits. Testable design of regular array architectures and PLAS: Testable design of regular array architectures and PLAS: the concept of C-testability.